VLSI architectures for the wavelet-based video coding system

Abstract

In the last decade there has been an increasing need for video compression in many multimedia applications such as desktop video conferencing, videophone, digital video recording, video-on-demand, and high-definition television(HDTV). The video coding system based on wavelet transform, namely, {\em wavelet-based video coding system\/} is promising due to its inherent multiresolution structure. In order to implement these video coding system in real time, the special-purpose VLSI is inevitable choice. In this thesis, we discuss efficient VLSI architectures for the wavelet-based video coding system; mainly for {\em wavelet transform} and {\em motion estimation}. We propose an efficient architecture for 1-D wavelet transform. We present a regular output scheduling for 1-D wavelet transform and systematic systolic mapping into linear array. The main features of our architecture include systolic computation, modularity, regularity, and cascadability. While the conventional systolic scheme has a throughput of period 2N, the proposed architecture has a throughput of period N maintaining the systolic structure where N is number of inputs. We also present the minimization of the number of local interconnections for the feedback data link. We propose a parallel systolic architecture for 2-D wavelet transform. We derive the architecture by using new computing scheme called {\em Row-and-then-Column}, and by applying systematic synthesis procedure with regular output scheduling. The proposed architecture consists of row-directional wavelet transform block and column-directional wavelet transform block. Each block is 2-D mesh-like array with regular interconnections. The area cost of the proposed architecture is 4pq MACs(multipliers and adders) that is more efficient than conventional architectures where p is the wavelet filter size and q is the number of parallel inputs. Furthermore, the proposed architecture has high regularity and modularity which brings down the design c...