DC Field | Value | Language |
---|---|---|
dc.contributor.author | Gouk, Donghyun | ko |
dc.contributor.author | Kang, Seungkwan | ko |
dc.contributor.author | Bae, Hanyeoreum | ko |
dc.contributor.author | Ryu, Eojin | ko |
dc.contributor.author | Lee, Sangwon | ko |
dc.contributor.author | Kim, Dongpyung | ko |
dc.contributor.author | Jang, Junhyeok | ko |
dc.contributor.author | Jung, Myoungsoo | ko |
dc.date.accessioned | 2024-09-11T19:00:12Z | - |
dc.date.available | 2024-09-11T19:00:12Z | - |
dc.date.created | 2024-06-16 | - |
dc.date.issued | 2024-07-09 | - |
dc.identifier.citation | The 16th ACM Workshop on Hot Topics in Storage and File Systems | - |
dc.identifier.uri | http://hdl.handle.net/10203/322920 | - |
dc.description.abstract | This work introduces a GPU storage expansion solution utilizing CXL, featuring a novel GPU system design with multiple CXL root ports for integrating diverse storage media (DRAMs and/or SSDs). We developed and siliconized a custom CXL controller integrated at the hardware RTL level, achieving two-digit nanosecond roundtrip latency, the first in the field. This study also includes speculative read and deterministic store mechanisms to efficiently manage read and write operations to hide the endpoint's backend media latency variation. Performance evaluations reveal our approach significantly outperforms existing methods, marking a substantial advancement in GPU storage technology. | - |
dc.language | English | - |
dc.publisher | Association for Computing Machinery, Inc | - |
dc.title | Breaking Barriers: Expanding GPU Memory with Sub-Two Digit Nanosecond Latency CXL Controller | - |
dc.type | Conference | - |
dc.type.rims | CONF | - |
dc.citation.publicationname | The 16th ACM Workshop on Hot Topics in Storage and File Systems | - |
dc.identifier.conferencecountry | US | - |
dc.identifier.conferencelocation | Santa Clara, CA | - |
dc.contributor.localauthor | Jung, Myoungsoo | - |
dc.contributor.nonIdAuthor | Lee, Sangwon | - |
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