FPGA-Accelerated Data Preprocessing for Personalized Recommendation Systems

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dc.contributor.authorKim, Hyeseongko
dc.contributor.authorLee, Yunjaeko
dc.contributor.authorRhu, Minsooko
dc.date.accessioned2024-09-03T10:00:13Z-
dc.date.available2024-09-03T10:00:13Z-
dc.date.created2024-08-29-
dc.date.issued2024-01-
dc.identifier.citationIEEE COMPUTER ARCHITECTURE LETTERS, v.23, no.1, pp.9 - 10-
dc.identifier.issn1556-6056-
dc.identifier.urihttp://hdl.handle.net/10203/322585-
dc.description.abstractDeep neural network (DNN)-based recommendation systems (RecSys) are one of the most successfully deployed machine learning applications in commercial services for predicting ad click-through rates or rankings. While numerous prior work explored hardware and software solutions to reduce the training time of RecSys, its end-to-end training pipeline including the data preprocessing stage has received little attention. In this work, we provide a comprehensive analysis of RecSys data preprocessing, root-causing the feature generation and normalization steps to cause a major performance bottleneck. Based on our characterization, we explore the efficacy of an FPGA-accelerated RecSys preprocessing system that achieves a significant 3.4-12.1x end-to-end speedup compared to the baseline CPU-based RecSys preprocessing system.-
dc.languageEnglish-
dc.publisherIEEE COMPUTER SOC-
dc.titleFPGA-Accelerated Data Preprocessing for Personalized Recommendation Systems-
dc.typeArticle-
dc.identifier.wosid001165793400001-
dc.identifier.scopusid2-s2.0-85179040384-
dc.type.rimsART-
dc.citation.volume23-
dc.citation.issue1-
dc.citation.beginningpage9-
dc.citation.endingpage10-
dc.citation.publicationnameIEEE COMPUTER ARCHITECTURE LETTERS-
dc.identifier.doi10.1109/LCA.2023.3336841-
dc.contributor.localauthorRhu, Minsoo-
dc.contributor.nonIdAuthorKim, Hyeseong-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorPersonalized recommendation system-
dc.subject.keywordAuthordata preprocessing-
dc.subject.keywordAuthortraining-
dc.subject.keywordAuthorFPGA-
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