DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Taeyeong | ko |
dc.contributor.author | Lee, Jungchul | ko |
dc.date.accessioned | 2024-09-03T10:00:09Z | - |
dc.date.available | 2024-09-03T10:00:09Z | - |
dc.date.created | 2024-08-29 | - |
dc.date.issued | 2024-06 | - |
dc.identifier.citation | MICROELECTRONIC ENGINEERING, v.289 | - |
dc.identifier.issn | 0167-9317 | - |
dc.identifier.uri | http://hdl.handle.net/10203/322582 | - |
dc.description.abstract | Nanoscale stencil lithography, providing sub -micrometer resolutions, is being implemented as a reliable patterning technique within the nanotechnology domain. Despite their advantages such as no resist processing, easy manipulation and reusability, patterning using a nanoscale stencil often faces challenges due to the gap between the nanoscale stencil and the substrate. This tends to result in unwanted pattern blurring, typically dimension wider than intended design. To address this issue, we minimize the gap by conformally attaching the nanoscale stencil to the substrate, thereby effectively eliminating a key factor contributing to the blurring effect. The nanoscale stencil is fabricated by forming nanoslits on the 50 nm thick Silicon -on -Nothing (SON) membrane with perforations, using focused ion beam (FIB) milling. The transfer of this stencil onto a substrate enables conformal adhesion due to its 1012 times lower flexural rigidity of the stencil compared to bulk silicon. Upon deposition of chromium and gold through the transferred stencil, a metal pattern array with the full width at half maximum (FWHM) of 43 nm is produced, demonstrating the potential of our approach for fabricating uniform nanoscale patterns with enhanced pattern resolution. | - |
dc.language | English | - |
dc.publisher | ELSEVIER | - |
dc.title | Fabrication of nanoscale stencils through focused ion beam milling and dry transfer of silicon-on-nothing membrane with perforations | - |
dc.type | Article | - |
dc.identifier.wosid | 001218339300001 | - |
dc.identifier.scopusid | 2-s2.0-85188136711 | - |
dc.type.rims | ART | - |
dc.citation.volume | 289 | - |
dc.citation.publicationname | MICROELECTRONIC ENGINEERING | - |
dc.identifier.doi | 10.1016/j.mee.2024.112172 | - |
dc.contributor.localauthor | Lee, Jungchul | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Stencil lithography | - |
dc.subject.keywordAuthor | Silicon-on-nothing | - |
dc.subject.keywordAuthor | Nanofabrication | - |
dc.subject.keywordAuthor | High temperature annealing | - |
dc.subject.keywordPlus | LITHOGRAPHY | - |
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