DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chung, Jae-Hyun | ko |
dc.contributor.author | Kim, Ye-Dam | ko |
dc.contributor.author | Park, Chang-Un | ko |
dc.contributor.author | Park, Kun-Woo | ko |
dc.contributor.author | Oh, Dong-Ryeol | ko |
dc.contributor.author | Seo, Min-Jae | ko |
dc.contributor.author | Ryu, Seung-Tak | ko |
dc.date.accessioned | 2024-09-03T07:00:16Z | - |
dc.date.available | 2024-09-03T07:00:16Z | - |
dc.date.created | 2024-08-29 | - |
dc.date.issued | 2024-08 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.59, no.8, pp.2481 - 2491 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/322564 | - |
dc.description.abstract | This article presents an energy-efficient high-resolution dual-residue (D-R) pipelined-successive approximation register (SAR) analog-to-digital converter (ADC), with a backend capacitive interpolating SAR ADC incorporated with noise-shaping (NS) capability. The residue amplifier design could be simplified as the residue is pre-amplified by the amplifier for the kT/C-noise cancellation. Moreover, the proposed segmented digital-to-analog converter (DAC) structure overcomes parasitic capacitance limitations in the capacitive interpolation, improving resolution along with the gain-error-free advantage of the D-R structure. Fabricated in a 180-nm CMOS technology, the prototype ADC achieves an 81.2-dB signal-to-noise and distortion ratio (SNDR) and an 89.9-dB spurious-free dynamic range (SFDR) in a 1.5-MHz bandwidth (BW) at an over-sampling ratio (OSR) of 8 with a 170.4-dB SNDR Schreier figure-of-merit (FoM) without any calibration. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A 1.5-MHz BW 81.2-dB SNDR Dual-Residue Pipeline ADC With a Fully Dynamic Noise-Shaping Interpolating-SAR ADC | - |
dc.type | Article | - |
dc.identifier.wosid | 001164195600001 | - |
dc.identifier.scopusid | 2-s2.0-85187299697 | - |
dc.type.rims | ART | - |
dc.citation.volume | 59 | - |
dc.citation.issue | 8 | - |
dc.citation.beginningpage | 2481 | - |
dc.citation.endingpage | 2491 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/JSSC.2024.3360944 | - |
dc.contributor.localauthor | Ryu, Seung-Tak | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Analog-to-digital converter (ADC) | - |
dc.subject.keywordAuthor | capacitive interpolation | - |
dc.subject.keywordAuthor | high-resolution dual-residue (D-R) pipelined-successive approximation register (SAR) analog-to-digital converter (ADC) | - |
dc.subject.keywordAuthor | inter-stage gain error | - |
dc.subject.keywordAuthor | kT/ C noise cancellation | - |
dc.subject.keywordAuthor | noise shaping (NS) | - |
dc.subject.keywordAuthor | quantization leakage error | - |
dc.subject.keywordAuthor | SAR-ADC | - |
dc.subject.keywordAuthor | segmented digital-to-analog converter (DAC) | - |
dc.subject.keywordPlus | GAIN | - |
dc.subject.keywordPlus | DB | - |
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