Signal integrity analysis, design, and modeling of high speed and low power Through-Silicon Via (TSV) enablers for next-generation High-Bandwidth Memory (HBM)

Abstract

In this study, for the development of next-generation HBM, high speed and low power TSV are proposed. This paper comprehensively presents design, signal integrity analysis, and modeling from an electrical perspective. The proposed TSV enablers consist of two main components. First, the TSV with the silicon dioxide well (SDW) is proposed to reduce leakage current by inserting SDW into the silicon substrate and mitigate impedance drop issues by decreasing the effective dielectric constant. Furthermore, the proposed TSV with SDW decreases parasitic capacitance in the I/O channel. Second, for the high-stack and high-speed HBM, the TSV with the passive equalizer (PEQ) is proposed to mitigate the inter-symbol-interference (ISI), and suppress crosstalk by increasing the self-inductance in the inductive coupling region. The two proposed TSV enablers can be mutually complementary when applied simultaneously for the design of the next-generation HBM. Finally, the proposed TSV enablers are verified compared with the conventional structure.