(A) process-scalable sleep timer IC for ultra-low-power IoT applications

Abstract

The growth of the battery-powered wireless market, especially in the context of IoT and biomedical applications, has driven the demand for ultra-low-power (ULP) wireless systems. These ULP systems have a wide range of applications, from bio-signal acquisition devices to smart homes and factories. Efficient energy management is critical for ULP wireless systems due to limited energy sources and high energy demands of radio transmission and computing. Duty cycling, which involves turning on specific system blocks only when needed, is a key strategy to conserve energy. The accuracy of the sleep timer, a crucial component in duty cycling, affects the overall energy consumption of ULP wireless nodes. Various types of sleep timers, such as crystal oscillators, MEMS oscillators, and on-chip sleep timers, are used to manage power consumption and accuracy. On-chip sleep timers can achieve accuracy better than $\pm$500 ppm with the help of lookup tables and temperature sensors. Additionally, on-chip sleep timers are cost-effective as compared to external crystal or MEMS oscillators. They eliminate the need for additional components, reducing the bill of materials (BOM) cost and simplifying the overall design. However, the impact of process scaling on on-chip sleep timers is a significant challenge. Process scaling leads to increased leakage currents, which affects the sleep timer's intrinsic temperature dependency. To address this issue, this dissertation proposes a new architectural-level change which is the ultra-low-voltage (ULV) sleep timer architecture. ULV architecture helps limit intrinsic temperature dependency, reducing the calibration burden, including temperature sensor resolution. In this dissertation, conventional FLL-based on-chip sleep timer architectures are classified into three types: voltage-domain, phase-domain, and current-domain. Each has its advantages and challenges, with voltage-domain being simple but challenging to implement in ULV, phase-domain offering in-situ temperature digitization but adding power overhead, and current-domain offering good temperature-dependence performance but being challenging in ULV due to VDD-hungry circuits. This dissertation presents a new on-chip sleep timer architecture, based on time-domain FLL, that is process-scalable. The proposed IC is built in ULV to limit intrinsic temperature dependency by suppressing leakage levels. It replaces VDD-hungry circuits with scalable ones, offers reference resistance multiplication without adding significant temperature dependency, and provides in-situ temperature digitization for LUT-based calibration.