Hold-up time compensation method for phase-shifted full-bridge converter using dual-active-clamp-snubber이중-능동-클램프-스너버를 사용한 위상천이 풀브리지 컨버터에서의 홀드업 시간 보상 기법

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In general, the power supply must regulate the output voltage for a time called the 'hold-up time' even when the AC input is lost. At this time, since the link capacitor voltage decreases as the energy stored in the link capacitor is used, the DC/DC converter must be designed to operate in a wide input range to ensure a hold-up time. This paper proposes a hold-up time compensation method for phase-shifted full-bridge (PSFB) converter using a dual-active-clamp-snubber. The proposed method allows the PSFB converter to operate at the maximum duty ratio in the nominal state, and the voltage gain between the nominal state and the hold-up state is continuous. Additionally, it can be designed with a high turns-ratio, low diode voltage rating, and a small output inductor. As a result, this reduces loss due to primary side current, diode conduction loss, and loss of the output inductor, leading to high efficiency. The validity of the proposed circuit was verified with a prototype converter designed with $300 \sim 400 V$ input and $56 V/715 W$ output.
Advisors
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Description
한국과학기술원 :전기및전자공학부,
Publisher
한국과학기술원
Issue Date
2024
Identifier
325007
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학부, 2024.2,[iv, 33 p. :]

Keywords

위상천이 풀브리지 컨버터▼a홀드업 시간▼a이중-능동-클랩프-스너버▼a고효율; Phase-shifted full-bridge converter▼aHold-up time▼aDual-active-clamp-snubber▼aHigh-efficiency

URI
http://hdl.handle.net/10203/321768
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=1097286&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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