(A) memory-efficient 3d reconstruction processor with dilation-based tsdf fusion and block-projection cache system for spatial computing

Abstract

A real-time dense 3D reconstruction on spatial computing is challenging since its memory access surpasses the available memory bandwidth. To solve this problem, the proposed processor integrates two key building blocks – Dilation-based TSDF (D-TSDF) fusion and Block-Projection (BP) engine. D-TSDF projects the depth map in the reverse order of voxel-to-pixel coordinate transformation and dilates it, leading to 96.61%p External Memory Access (EMA) reduction with minimum map quality degradation. Second, a specialized BP engine compresses high-resolution occupancy grid by decomposing the 3D bitmap into 2D and 1D vectors, achieving ×166.09 reduced memory bandwidth. The proposed processor is implemented in 28nm CMOS technology occupying 1.27 mm2 area. As a result, 96.45 fps 3D reconstruction is possible while consuming only 15.94 mW power.