(A) Study on bottom buffer layer thickness optimization for trench structure thin-film transistors트렌치 구조 박막 트랜지스터를 위한 하부 버퍼층 두께 최적화 연구

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dc.contributor.advisor박상희-
dc.contributor.authorKim, Kang-
dc.contributor.author김강-
dc.date.accessioned2024-07-30T19:31:16Z-
dc.date.available2024-07-30T19:31:16Z-
dc.date.issued2024-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=1096757&flag=dissertationen_US
dc.identifier.urihttp://hdl.handle.net/10203/321539-
dc.description학위논문(석사) - 한국과학기술원 : 신소재공학과, 2024.2,[vi, 40 p. :]-
dc.description.abstractOxide semiconductors are crucial for the display backplanes. The demand for high-mobility oxide TFTs is increasing due to driver circuit integration in display backplanes. High-mobility oxide semiconductors such as $In_2O_3$ are sensitive to the materials and deposition conditions of interfacing layers. Previously, $In_2O_3$ TFT using trench structure was fabricated using two different buffer layers. The role of bottom buffer layer was to create a conducting path inside the channel by modulating hydrogen and oxygen vacancy content of the adjacent $In_2O_3$ active layer. In this study, the thickness as well as material of the buffer layer is modulated to control the TFT characteristics. Increasing thickness of both $Al_2O_3$ and $SiO_2$ buffer layers resulted in more negative shift in VON, and the VON shift saturated at buffer layer thicknesses over 30 nm. Thin-film analysis revealed that hydrogen and oxygen vacancy diffusion from the buffer layers into the active layer occurred, and the amount of diffusion is dependent on the buffer layer thickness. Roughness of the films did not depend on the buffer layer thickness, and it was concluded that the diffusion of shallow donors is more dominant factor in VON shift.-
dc.languageeng-
dc.publisher한국과학기술원-
dc.subject버퍼층▼a얕은 도너▼a수소▼a산소 공공▼a확산-
dc.subjectBuffer layer▼aShallow donor▼aHydrogen▼aOxygen vacancy▼aDiffusion-
dc.title(A) Study on bottom buffer layer thickness optimization for trench structure thin-film transistors-
dc.title.alternative트렌치 구조 박막 트랜지스터를 위한 하부 버퍼층 두께 최적화 연구-
dc.typeThesis(Master)-
dc.identifier.CNRN325007-
dc.description.department한국과학기술원 :신소재공학과,-
dc.contributor.alternativeauthorPark, Sang-Hee-
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