Deep Reinforcement Learning-Based Optimal and Fast Hybrid Equalizer Design Method for High-Bandwidth Memory (HBM) Module

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In this article, we propose a deep reinforcement learning (DRL)-based optimal and fast hybrid equalizer (HYEQ) design method for high-bandwidth memory (HBM) module. The HYEQ is a promising key to improving the signal integrity (SI) performance along the broad frequency bands by combining a passive equalizer (PEQ) and an active equalizer (AEQ) for the HBM module. However, the equalizer design process is extremely complex because all of the parameters should be co-optimized by considering the SI characteristics of the target channel. To tackle the design complexity, we utilize the DRL method that trains the policy network to optimize the HYEQ design for maximizing an eye-opening (EO) value. The policy network is configured with a recurrent type of neural network and sequentially determines the optimal values of the HYEQ parameters by considering the relevance between the parameters. Furthermore, the training process for the policy network is implemented in diverse channel dimensions of the silicon interposer. By learning the feature between channel dimensions and equalizer parameters, the policy network directly designs the optimal HYEQ for arbitrary channel dimensions. For verification, the proposed method is compared with the random search (RS) and genetic algorithm (GA) in terms of optimality performance and computational time. The result shows that the proposed method outperforms both RS and GA.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2023-11
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, v.13, no.11, pp.1804 - 1816

ISSN
2156-3950
DOI
10.1109/TCPMT.2023.3317295
URI
http://hdl.handle.net/10203/320024
Appears in Collection
EE-Journal Papers(저널논문)
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