An Energy-Efficient Delay Insensitive Asynchronous Interface for Globally Asynchronous Locally Synchronous (GALS) System

Abstract

The process, voltage, and temperature (PVT) variations are significant factors that must be considered when designing chips, especially chips designed for edge devices. Typically, chip designers use an extra timing margin to guarantee the operation of the chip under the worst-case condition. However, this approach can lead to reduced performance and energy efficiency. A globally asynchronous locally synchronous system (GALS) is an alternative approach to ensure chip operation while maintaining performance. This paper presents an energy-efficient asynchronous interface with a delay-insensitive protocol for the GALS system. As the prior delay-insensitive interface consumes significant energy, low-swing signaling by stacking the voltage domain reduces energy consumption at little cost. In addition, adaptive timing control is implemented to support a long wire connection and improve interface robustness. As a result, the energy-efficient asynchronous interface implemented on 65nm technology consumed 1.6x less energy than the prior delay-insensitive asynchronous interface while being able to drive wire up to 1.25mm long.