DC Field | Value | Language |
---|---|---|
dc.contributor.author | Shin, Seunghwa | ko |
dc.contributor.author | Kang, Gyeong-Gu | ko |
dc.contributor.author | Lim, Gyu-Wan | ko |
dc.contributor.author | Kim, Hyun-Sik | ko |
dc.date.accessioned | 2024-04-04T01:00:17Z | - |
dc.date.available | 2024-04-04T01:00:17Z | - |
dc.date.created | 2024-04-04 | - |
dc.date.created | 2024-04-04 | - |
dc.date.issued | 2024-04 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.59, no.4, pp.1050 - 1066 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/318957 | - |
dc.description.abstract | This article presents an area-efficient 10-bit source-driver IC (SD-IC) for mobile displays. Addressing the challenge of exponential die area growth associated with higher digital-to-analog converter (DAC) resolution dominating color depth, we propose a three-stage-cascading interpolation design solution. In the first stage, a two-output voltage selector selects adjacent voltages from the global resistor string. The proposed overlap-switch merging (OSM) technique reduces its size by two times compared to conventional two-output selectors. The second-stage interpolation employs a successive-approximation-register (SAR)-interpolating switched-capacitor (SI-SC) DAC, enhanced with bit-adaptive switch-size (BASS) modulation to minimize the switching errors. The proposed SI-SC DAC also features an intrinsic two-output design for further interpolation in the subsequent stage. In the last (third) stage, a super-class-AB operational transconductance amplifier (OTA)-based buffer amplifier performs accurate 1-bit true-dc interpolation with no overhead while driving the final output with a fast slew rate. The prototype chip was fabricated in a 180-nm 1.8/5-V CMOS process. The maximum differential nonlinearity (DNL) and integral nonlinearity (INL) were measured to be -0.37 and 1.17 LSB, respectively, in a 10-bit resolution. The maximum deviation of voltage outputs (DVOs) achieved was 15.5 mV. The proposed chip exhibits a source channel size of 2211 um(2) , which is the smallest reported to date, along with a competitive slew rate of 44 V/mu s measured at C-Load= 100 pF. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A Display Source-Driver IC Featuring Multistage-Cascaded 10-Bit DAC and True-DC-Interpolative Super-OTA Buffer | - |
dc.type | Article | - |
dc.identifier.wosid | 001164055300001 | - |
dc.identifier.scopusid | 2-s2.0-85184801870 | - |
dc.type.rims | ART | - |
dc.citation.volume | 59 | - |
dc.citation.issue | 4 | - |
dc.citation.beginningpage | 1050 | - |
dc.citation.endingpage | 1066 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/jssc.2024.3350240 | - |
dc.contributor.localauthor | Kim, Hyun-Sik | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article; Early Access | - |
dc.subject.keywordAuthor | Bit-adaptive switch-size (BASS) modulation | - |
dc.subject.keywordAuthor | buffer amplifier | - |
dc.subject.keywordAuthor | deviation of voltage outputs (DVOs) | - |
dc.subject.keywordAuthor | die area efficiency | - |
dc.subject.keywordAuthor | digital-to-analog converter (DAC) | - |
dc.subject.keywordAuthor | display source driver | - |
dc.subject.keywordAuthor | slew rate | - |
dc.subject.keywordAuthor | super-class-AB | - |
dc.subject.keywordAuthor | switched-capacitor (SC) | - |
dc.subject.keywordAuthor | voltage interpolation | - |
dc.subject.keywordPlus | COLUMN-DRIVER | - |
dc.subject.keywordPlus | LOW-POWER | - |
dc.subject.keywordPlus | SLEW-RATE | - |
dc.subject.keywordPlus | AMPLIFIER | - |
dc.subject.keywordPlus | AREA | - |
dc.subject.keywordPlus | ARCHITECTURE | - |
dc.subject.keywordPlus | COMPACT | - |
dc.subject.keywordPlus | SCHEME | - |
dc.subject.keywordPlus | RDACS | - |
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