Heterogeneous 3-D Sequential CFETs With Ge (110) Nanosheet p-FETs on Si (100) Bulk n-FETs

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In this study, we report on the fabrication and characterization of 3-D sequential complementary fieldeffect-transistors (CFETs) using the direct wafer bonding (DWB) technology and a low-temperature process for monolithic 3-D (M3D) integration. The device features a high-performance top Ge (110)/(110) channel on a bottom Si CMOS. To ensure high performance without causing damage to the bottom Si n-FETs, the maximum thermal budget during the fabrication of the top Ge p-FETs was limited to 400 C-degrees. We systematically investigated the mobility enhancement of the thin Ge (110) nanosheet (NS) channel p-FETs as a function of channel orientation. Our results demonstrate that the low effective hole mass along the (110) direction on Ge (110) wafer provides record-high mobility of 400 cm(2)/V<middle dot>s (corresponding to 760 cm(2)/V<middle dot>s when normalized by footprint) at room temperature, which is the highest reported among the Ge p-FETs with similar channel thicknesses.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2024-01
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON ELECTRON DEVICES, v.71, no.1, pp.393 - 399

ISSN
0018-9383
DOI
10.1109/TED.2023.3331669
URI
http://hdl.handle.net/10203/317876
Appears in Collection
EE-Journal Papers(저널논문)
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