A DRAM-Based Process-in-Memory Using Data Redundancy and Differential Bit-Line Computation

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This paper presents a novel Dynamic Random Access Memory (DRAM) - In Memory Computing (IMC) structure achieving high throughput without altering the existing cell configuration. Multiple Word Line (WL) activations are utilized to enhance the throughput of Multiply and Accumulate (MAC) operations. The issue of data destruction during simultaneous WL activations is addressed by employing the adjacent MAT and differential operation of the sense amplifier. Moreover, the problem arising from non-ideality in WL switches is alleviated through the differential bit-line computation operation. Consequently, an accuracy of 99.01% was achieved on the MNIST dataset.
Publisher
한국과학기술원 반도체설계교육센터
Issue Date
2024-01
Language
English
Citation

IDEC Journal of Integrated Circuits and Systems, v.10, no.1

DOI
10.23075/jicas.2024.10.1.002
URI
http://hdl.handle.net/10203/317116
Appears in Collection
EE-Journal Papers(저널논문)
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