A DRAM-Based Process-in-Memory Using Data Redundancy and Differential Bit-Line Computation

Abstract

This paper presents a novel Dynamic Random Access Memory (DRAM) - In Memory Computing (IMC) structure achieving high throughput without altering the existing cell configuration. Multiple Word Line (WL) activations are utilized to enhance the throughput of Multiply and Accumulate (MAC) operations. The issue of data destruction during simultaneous WL activations is addressed by employing the adjacent MAT and differential operation of the sense amplifier. Moreover, the problem arising from non-ideality in WL switches is alleviated through the differential bit-line computation operation. Consequently, an accuracy of 99.01% was achieved on the MNIST dataset.