Design and Analysis of Double-side Characteristic Impedance Compensation Structure in 2.5D / 3D Package for High-speed Serial Link

Abstract

A double-side characteristic impedance compensation structure for a 2. 5D/3D package is proposed and designed to mitigate the impedance discontinuity caused by the controlled collapse chip connection (C4)-bump. The compensation structures applicable to the interposer and package (PKG) were designed. The insertion loss according to the variables of the structure is analyzed. The insertion loss and eye-height are improved through reflection reduction of the proposed double-side compensation structure compared to the one-side compensation structure. The insertion loss is improved by 5.6% and 9.8% at 32 GHz and 64 GHz, respectively. The eye-height is improved by 2.5% and 12.5% at 128 Gbps and 256 Gbps, respectively.