Multisource Clock Tree Synthesis Through Sink Clustering and Fast Clock Latency Prediction

Abstract

Multisource clock tree consists of a number of local clock trees rooted at respective tap drivers, which are then connected to a clock source through H-tree. We address two key problems for the synthesis of multisource clock tree: clock sink clustering for constructing local clock trees, and the decision of the number of trees. Weight-balanced k-means clustering is applied for the first problem; sinks of the same cluster are localized and the load capacitances of tap drivers are balanced as much as possible. The number of trees can be searched in exhaustive fashion, while clock latency of local trees is estimated with fast CNN-based model. Experiments with a few test circuits demonstrate that clock latency is reduced by 11.8 % on average, while synthesis runtime is reduced by 64% thanks to CNN model.