DC Field | Value | Language |
---|---|---|
dc.contributor.author | Oh, Sein | ko |
dc.contributor.author | Park, Seunga | ko |
dc.contributor.author | Jung, Yoontae | ko |
dc.contributor.author | Koo, Jimin | ko |
dc.contributor.author | Cho, Donghee | ko |
dc.contributor.author | Ha, Sohmyung | ko |
dc.contributor.author | Je, Minkyu | ko |
dc.date.accessioned | 2023-12-04T07:02:06Z | - |
dc.date.available | 2023-12-04T07:02:06Z | - |
dc.date.created | 2023-11-29 | - |
dc.date.issued | 2023-06-11 | - |
dc.identifier.citation | 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) | - |
dc.identifier.uri | http://hdl.handle.net/10203/315687 | - |
dc.description.abstract | A 4th-order passive bandpass Δ Σ modulator (BPDSM) using a 2- path transformation structure is presented. The proposed BPDSM replaces a power-hungry resonator with a z-to-z2-transformed passive loop filter. The prototype bandpass Δ Σ ADC provides a wide intermediate frequency (IF) range of 1.25MHz to 60MHz. The measured SNDR is 69dB with a power consumption of 2.5mW at 12MHz bandwidth when its highest sampling rate is 240MS/s. | - |
dc.language | English | - |
dc.publisher | IEEE | - |
dc.title | A 2.5mW 12MHz-BW 69dB SNDR Passive Bandpass ΔΣ ADC with Highpass Noise-Shaping SAR Quantizers | - |
dc.type | Conference | - |
dc.identifier.scopusid | 2-s2.0-85167589309 | - |
dc.type.rims | CONF | - |
dc.citation.publicationname | 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) | - |
dc.identifier.conferencecountry | JA | - |
dc.identifier.conferencelocation | Kyoto | - |
dc.identifier.doi | 10.23919/vlsitechnologyandcir57934.2023.10185342 | - |
dc.contributor.localauthor | Je, Minkyu | - |
dc.contributor.nonIdAuthor | Park, Seunga | - |
dc.contributor.nonIdAuthor | Jung, Yoontae | - |
dc.contributor.nonIdAuthor | Koo, Jimin | - |
dc.contributor.nonIdAuthor | Cho, Donghee | - |
dc.contributor.nonIdAuthor | Ha, Sohmyung | - |
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