A 7–8.5 GHz LC Voltage-Controlled Oscillator with –111.7 dBc/Hz Phase Noise at 1-MHz offset for Ultra-Low-Jitter Phase-Locked Loop

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DC FieldValueLanguage
dc.contributor.author조용우ko
dc.contributor.author채문재ko
dc.contributor.author최재혁ko
dc.date.accessioned2023-12-01T07:02:24Z-
dc.date.available2023-12-01T07:02:24Z-
dc.date.created2023-12-01-
dc.date.issued2023-01-
dc.identifier.citationIDEC Journal of Integrated Circuits and Systems, v.9, no.1, pp.1 - 5-
dc.identifier.urihttp://hdl.handle.net/10203/315595-
dc.description.abstractThis work presents an area efficiency LC voltage-controlled oscillator for an ultra-low-jitter phase-locked loop. Using a 3-turn area-compact spiral, the VCO achieve area-efficient without degrading LC-tank quality factor. The negative transconductance cell was NMOS type so that the start-up was done in 3ns. This work also includes a tail inductor for the noise filtering. As a result, the measured phase noise at 8 GHz was -111.7 dBc/Hz with 1 MHz offset and -134.9 dBc/Hz with 10 MHz offset. The power consumption was only 2.7 mW at 8 GHz. Also, the die area was less than 0.03 mm2.-
dc.languageEnglish-
dc.publisher한국과학기술원 반도체설계교육센터-
dc.titleA 7–8.5 GHz LC Voltage-Controlled Oscillator with –111.7 dBc/Hz Phase Noise at 1-MHz offset for Ultra-Low-Jitter Phase-Locked Loop-
dc.typeArticle-
dc.type.rimsART-
dc.citation.volume9-
dc.citation.issue1-
dc.citation.beginningpage1-
dc.citation.endingpage5-
dc.citation.publicationnameIDEC Journal of Integrated Circuits and Systems-
dc.identifier.doi10.23075/jicas.2023.9.1.001-
dc.identifier.kciidART002916377-
dc.contributor.localauthor최재혁-
dc.contributor.nonIdAuthor채문재-
dc.description.isOpenAccessN-
dc.subject.keywordAuthorArea-efficient-
dc.subject.keywordAuthorJitter-
dc.subject.keywordAuthorLC-Oscillator-
dc.subject.keywordAuthorPhase-Locked Loop-
dc.subject.keywordAuthorTail inductor-
dc.subject.keywordAuthorVoltage-Controlled Oscillator (VCO)-
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