A Low-jitter Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Optimally Spaced TDC for Flicker-Noise Reduction

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dc.contributor.authorHwang, Chan woongko
dc.contributor.authorPark, Hangiko
dc.contributor.authorLee, Yongsunko
dc.contributor.authorSeong, Taehoko
dc.contributor.authorChoi, Jaehyoukko
dc.date.accessioned2023-12-01T02:00:24Z-
dc.date.available2023-12-01T02:00:24Z-
dc.date.created2023-12-01-
dc.date.issued2023-10-
dc.identifier.citationIDEC Journal of Integrated Circuits and Systems, v.9, no.4, pp.37 - 43-
dc.identifier.urihttp://hdl.handle.net/10203/315533-
dc.description.abstractThis work presents a low-jitter ring-oscillator-based digital PLL (RO-DPLL). To achieve low jitter, the proposed RO-DPLL used calibration techniques to optimize the gain of the Proportional-path (P-path) and Integral-path (I-path) in the digital-loop-filter (DLF) simultaneously. Since the effect of flicker noise increases as the frequency increases, the frequency drift of the RO-DPLL becomes more severe in the operation of the RO-DPLL. Thus, it is critical to calibrate the gain of the I-path to an optimal value because I-path of DLF compensates for the frequency error of the PLL. Moreover, the optimally-spaced time-to-digital-converter (OS-TDC) with the threshold calibrator provides sufficient information, supporting the efficient operation of the calibrators. Due to the use of the P/I-path co-optimization (PICO) and OS-TDC with calibrator, the proposed RO-DPLL achieved the rms jitter of 343 fs and the reference spur of –65dBc. And, its FoMjitter,N was –258.5 dBc, comparable to the state-of-the-art RO-based analog PLLs.-
dc.languageEnglish-
dc.publisher한국과학기술원 반도체설계교육센터-
dc.titleA Low-jitter Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Optimally Spaced TDC for Flicker-Noise Reduction-
dc.typeArticle-
dc.type.rimsART-
dc.citation.volume9-
dc.citation.issue4-
dc.citation.beginningpage37-
dc.citation.endingpage43-
dc.citation.publicationnameIDEC Journal of Integrated Circuits and Systems-
dc.identifier.doi10.23075/jicas.2023.9.4.008-
dc.identifier.kciidART002999466-
dc.contributor.localauthorChoi, Jaehyouk-
dc.contributor.nonIdAuthorLee, Yongsun-
dc.contributor.nonIdAuthorSeong, Taeho-
dc.description.isOpenAccessN-
dc.subject.keywordAuthorRing digitally-controlled oscillator (RDCO)-
dc.subject.keywordAuthordigital phase-locked-loop (DPLL)-
dc.subject.keywordAuthortime-to-digital converter (TDC)-
dc.subject.keywordAuthorproportional-path-
dc.subject.keywordAuthorintegral-path-
dc.subject.keywordAuthordigital-loop filter (DLF)-
dc.subject.keywordAuthorrms jitter-
dc.subject.keywordAuthorflicker noise-
dc.subject.keywordAuthorthermal noise-
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