DC Field | Value | Language |
---|---|---|
dc.contributor.author | Yun, Byeonghun | ko |
dc.contributor.author | Park, Dae-Woong | ko |
dc.contributor.author | Lee, Sang-Gug | ko |
dc.date.accessioned | 2023-11-16T02:01:10Z | - |
dc.date.available | 2023-11-16T02:01:10Z | - |
dc.date.created | 2023-10-11 | - |
dc.date.issued | 2023-11 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.58, no.11, pp.3089 - 3102 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/314751 | - |
dc.description.abstract | This article proposes high-gain, high-output-power, and high-power-added efficiency (PAE) power amplifiers (PAs) by adopting an output power maximized (OPM) maximum achievable gain ( G(max))-core with the transmission line (TL)-based zero-degree power combiners (ZDCs) and zero-degree splitters (ZDSs). By utilizing the proposed small- and large-signal twoport network parameter-based analysis for implementing the G(max)-core, the last-stage OPM G(max)-core can maximize largesignal output power and small-signal gain at the same time. In addition, by adopting the G(max)-concept in all amplifying stages, the amount of gain per stage can be maximized, leading to higher PAE. For implementing the low-loss power combining (PC) and splitting networks, ZDC and ZDS are adopted. By adopting the proposed OPM G(max)-core and ZDCs and ZDSs, six-stage 250-GHz two- and four-way PC PAs are implemented in a 65-nm CMOS process. The two PAs achieve P-sat of 9.2 and 10.5 dBm, OP1 dB of 6 and 7.7 dBm, PAE of 4.6% and 2.8%, and power gains of 28 and 26 dB at 245 and 243 GHz, respectively. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | H-Band Power Amplifiers in 65-nm CMOS by Adopting Output Power Maximized G(max)-Core and Transmission Line-Based Zero-Degree Power Networks | - |
dc.type | Article | - |
dc.identifier.wosid | 001060571300001 | - |
dc.identifier.scopusid | 2-s2.0-85168690976 | - |
dc.type.rims | ART | - |
dc.citation.volume | 58 | - |
dc.citation.issue | 11 | - |
dc.citation.beginningpage | 3089 | - |
dc.citation.endingpage | 3102 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/JSSC.2023.3299735 | - |
dc.contributor.localauthor | Lee, Sang-Gug | - |
dc.contributor.nonIdAuthor | Park, Dae-Woong | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | ~Amplifier | - |
dc.subject.keywordAuthor | CMOS | - |
dc.subject.keywordAuthor | gain boosting | - |
dc.subject.keywordAuthor | large-signal model | - |
dc.subject.keywordAuthor | maximum achievable gain (G(max)) | - |
dc.subject.keywordAuthor | power amplifier (PA) | - |
dc.subject.keywordAuthor | sub-terahertz (sub-THz) | - |
dc.subject.keywordPlus | P-SAT | - |
dc.subject.keywordPlus | WIDE-BAND | - |
dc.subject.keywordPlus | GAIN | - |
dc.subject.keywordPlus | SPECTROSCOPY | - |
dc.subject.keywordPlus | TECHNOLOGY | - |
dc.subject.keywordPlus | DESIGN | - |
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