DC Field | Value | Language |
---|---|---|
dc.contributor.author | Park, Minsik | ko |
dc.contributor.author | Song, Jonghyun | ko |
dc.contributor.author | Jeong, Jaeyong | ko |
dc.contributor.author | Lim, Jeong-Taek | ko |
dc.contributor.author | Song, Jae-Hyeok | ko |
dc.contributor.author | Lee, Won-Chul | ko |
dc.contributor.author | Sim, Gapseop | ko |
dc.contributor.author | Cho, Huijae | ko |
dc.contributor.author | Yoo, Dongeun | ko |
dc.contributor.author | Kang, Minho | ko |
dc.contributor.author | Ko, Hyoungho | ko |
dc.contributor.author | Lee, Jooseok | ko |
dc.contributor.author | Yang, Kyounghoon | ko |
dc.contributor.author | Kim, Choul-Young | ko |
dc.contributor.author | Kim, Youngsu | ko |
dc.contributor.author | Sul, Woo-Suk | ko |
dc.contributor.author | Kim, Sanghyeon | ko |
dc.contributor.author | Lee, Jongwon | ko |
dc.date.accessioned | 2023-10-29T09:01:29Z | - |
dc.date.available | 2023-10-29T09:01:29Z | - |
dc.date.created | 2023-09-04 | - |
dc.date.issued | 2023-10 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON ELECTRON DEVICES, v.70, no.10, pp.5257 - 5264 | - |
dc.identifier.issn | 0018-9383 | - |
dc.identifier.uri | http://hdl.handle.net/10203/313845 | - |
dc.description.abstract | In this article, we have demonstrated a simple 200-mm Si CMOS process-based integrated passive device (IPD) stack for millimeter-wave (mmW) monolithic 3-D (M3D) integration. By developing a double chemical mechanical polishing (CMP) technique for the final intermetal dielectric (IMD) process, an rms value of less than 1 nm for the top-surface roughness of the IPD stack was achieved, resulting in uniform 3-D integration of a 100-nm-thick active layer of the InGaAs high-electron-mobility transistor (HEMT) on the stack. The stack included a trap-rich layer (TRL) and a buried oxide layer (BOX) with a high-resistance Si substrate (HRS) to achieve high-frequency properties. The TRL and BOX were optimized to keep wafer bowing as low as possible while minimizing the radio frequency (RF) loss. A fabricated coplanar waveguide (CPW) based on a TRL with poly-Si deposited by low-pressure chemical vapor deposition (LP-CVD) and a BOX with SiO $_\text{2}$ deposited by LP-CVD exhibited an insertion loss (IL) value of 0.77 dB/mm at 40 GHz. IL values of the developed CPW were comparable to those of CMOS foundries, despite using thinner metal thickness, under a condition of the same metal width. The fabricated passive devices showed good quality factor (Q) characteristics sufficient to be utilized up to the V-band. In particular, the maximum Q values of the inductors are the best among Si lumped inductors reported in the mmW bands to date. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | 200-mm Si CMOS Process-Compatible Integrated Passive Device Stack for Millimeter-Wave Monolithic 3-D Integration | - |
dc.type | Article | - |
dc.identifier.wosid | 001051283400001 | - |
dc.identifier.scopusid | 2-s2.0-85168272886 | - |
dc.type.rims | ART | - |
dc.citation.volume | 70 | - |
dc.citation.issue | 10 | - |
dc.citation.beginningpage | 5257 | - |
dc.citation.endingpage | 5264 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
dc.identifier.doi | 10.1109/TED.2023.3302817 | - |
dc.contributor.localauthor | Yang, Kyounghoon | - |
dc.contributor.localauthor | Kim, Sanghyeon | - |
dc.contributor.nonIdAuthor | Park, Minsik | - |
dc.contributor.nonIdAuthor | Song, Jonghyun | - |
dc.contributor.nonIdAuthor | Lim, Jeong-Taek | - |
dc.contributor.nonIdAuthor | Song, Jae-Hyeok | - |
dc.contributor.nonIdAuthor | Lee, Won-Chul | - |
dc.contributor.nonIdAuthor | Sim, Gapseop | - |
dc.contributor.nonIdAuthor | Cho, Huijae | - |
dc.contributor.nonIdAuthor | Yoo, Dongeun | - |
dc.contributor.nonIdAuthor | Kang, Minho | - |
dc.contributor.nonIdAuthor | Ko, Hyoungho | - |
dc.contributor.nonIdAuthor | Lee, Jooseok | - |
dc.contributor.nonIdAuthor | Kim, Choul-Young | - |
dc.contributor.nonIdAuthor | Kim, Youngsu | - |
dc.contributor.nonIdAuthor | Sul, Woo-Suk | - |
dc.contributor.nonIdAuthor | Lee, Jongwon | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | CMOS-compatible | - |
dc.subject.keywordAuthor | heterogeneous integration | - |
dc.subject.keywordAuthor | integrated passive device (IPD) | - |
dc.subject.keywordAuthor | millimeter wave (mmW) | - |
dc.subject.keywordAuthor | monolithic 3-D (M3D) | - |
dc.subject.keywordPlus | SILICON | - |
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