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College of Engineering(공과대학)School of Electrical Engineering(전기및전자공학부)EE-Journal Papers(저널논문)

Path metric memory management for minimising interconnections in Viterbi decoders

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dc.contributor.authorKim, SYko
dc.contributor.authorKim, Hko
dc.contributor.authorPark, In-Cheolko
dc.date.accessioned2008-02-21T03:22:44Z-
dc.date.available2008-02-21T03:22:44Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2001-07-
dc.identifier.citationELECTRONICS LETTERS, v.37, no.14, pp.925 - 926-
dc.identifier.issn0013-5194-
dc.identifier.urihttp://hdl.handle.net/10203/3124-
dc.description.abstractTo simplify the interconnection between processing elements and path metric memory banks in Viterbi decoders, a new path metric update scheme is proposed based on two techniques, named swapped state grouping and swapped computing. The proposed scheme leads to a simple interconnection consisting of 2 x 2 switches.-
dc.description.sponsorshipThis work was supported in part by the Korea Science and Engineering Foundation through the MICROS Center at KAIST, Korea.en
dc.languageEnglish-
dc.language.isoen_USen
dc.publisherIEE-INST ELEC ENG-
dc.titlePath metric memory management for minimising interconnections in Viterbi decoders-
dc.typeArticle-
dc.identifier.wosid000169821800041-
dc.identifier.scopusid2-s2.0-0035811651-
dc.type.rimsART-
dc.citation.volume37-
dc.citation.issue14-
dc.citation.beginningpage925-
dc.citation.endingpage926-
dc.citation.publicationnameELECTRONICS LETTERS-
dc.embargo.liftdate9999-12-31-
dc.embargo.terms9999-12-31-
dc.contributor.localauthorPark, In-Cheol-
dc.contributor.nonIdAuthorKim, SY-
dc.contributor.nonIdAuthorKim, H-
dc.type.journalArticleArticle-
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