A Process-Scalable Ultra-Low-Voltage 180kHz Sleep Timer with a Time-Domain Amplifier and a Switch-less Resistance Multiplier

Abstract

An energy-efficient precise on-chip sleep timer is a key enabler of wireless SoCs for the internet of things (IoT). The intrinsic temperature dependency of the sleep timer determines the energy efficiency of the overall sleep timer system. Thus, having a lookup table (LUT) with a temperature sensor for calibration is inevitable to accomplish the high accuracy sleep timer required for wireless sensor nodes [1]-[3]. Also, having a sub-MHz-range frequency output is important because the sleep timer counts the ms-order time duration while being always on. Process scalability is another essential requirement to be integrated into wireless SoCs for IoT due to radio and processor performances, overall power efficiency, and die cost. However, process scaling results in an exponential increase of leakage currents, which are a major contributor to temperature dependency in sub- mu W on-chip sleep timers because they change exponentially with temperature. In this work, we present an ultra-lowvoltage (ULV) sleep timer architecture based on a frequency-locked loop (FLL). This ULV architecture limits the intrinsic temperature dependency of the on-chip FLL by exponentially suppressing the leakage level. The proposed ULV FLL also has an in-situ temperature readout function for LUT-based calibration.