Design methodology of passive equalizer for GDDR6 memory test

Abstract

As the data rate of Graphics Double Date Rate 6 memory (GDDR6) now exceeds 16 Gbps, it is becoming more important to test for high reliability. Especially, test interposer design to ensure GDDR6 memory operation and satisfy the target specifications at the test point is challenge due to the limitation of the design variation. In this paper, we propose a design methodology of L-R passive equalizer to achieve the normal operation and target specification of the GDDR6 memory test. The proposed design methodology is motivated from the voltage variation difference between GDDR6 and test point. Using the voltage trade-off, the additional amount of voltage obtained from the variation of test interposer design is used for equalization. The proposed passive equalizer design is verified in frequency and time domain simulations. It achieved not only the normal operation of the GDDR6, but also improved the eye opening of 24% and the timing jitter of 40.9%. The proposed design methodology of passive equalizer is cost effective, directly applicable and it can provide a high design flexibility for GDDR6 test interposer.