A Reverse-Feeding Hold-up Time Strategy for Two-Stage Grid-Interface PFC with a Rectifier-Coupled Boost Inductor

Abstract

This paper presents a reverse-feeding hold-up time strategy to improve the performance of two-stage grid-interface power factor correction (PFC) circuit with a rectifier-coupled boost inductor. During the hold-up time, instead of delivering the energy only through the dc-dc converter (e.g., a LLC converter, or a phase-shift full-bridge (PSFB) converter), the energy stored in the energy-buffer capacitor is also transferred through an extra-winding on the boost inductor to the secondary side. This additional energy transfer path regulates the output voltage during the hold-up time and offers extra flexibility to optimize the system performance during normal operation and hold-up time. With this configuration, the dc-dc converter can be designed as a almost fixed ratio dc transformer. The reverse-feeding strategy can extend the HUT by 25%, reduce the energy-buffer capacitor size by 25%, improve the system peak efficiency (96.5%) and enhance the power density. The effectiveness of the proposed method is verified by a PFC prototype with 100V-240Vrms ac input and 800W, 12V/66.7A dc output.