Design of CMOS receivers for 5G NR and LPWAN applications

Abstract

This dissertation discusses the design of CMOS receivers (RX) for two applications: (i) high performance 5G NR and (ii) low power wide area network (LPWAN) Internet-of-Things (IoT). For 5G application, an n79 (4.4 GHz - 5.0 GHz) variable gain LNA is presented. To offer a wide gain range while preserving good linearity with minimum power dissipation at lower gain modes, the proposed LNA adopted three key techniques: (i) imbalanced current bleeding, (ii) drain-side DC current switching and (iii) bleeding with an adaptive biasing scheme. The proposed LNA shows a peak gain of 20.5 dB with a 0.74 dB minimum NF, with a 13.4 dB gain control range while reducing the power down to 4.2 mW at the lowest gain mode. The proposed adaptive biasing improves the IIP3 by 4 dB. As a result, this LNA work achieves the best FoM1 among reported LNAs operating at 4-6 GHz. In addition, for LPWAN IoT application, a multi-band ultra-low-power binary frequency-shift keying (BFSK) RX is presented. For the front-end of the RX, it adopted a resistive feedback LNA with a tunable passive matching gain covering 0.2 - 1.0 GHz. The N-path filter based 50%-to-25% duty-cycle conversion mixer can further offer a 5-dB passive voltage gain. A frequency-to-energy BFSK demodulator is adopted with multi-channel selectivity. The proposed RX measured a -96 dBm sensitivity with 295 uW dissipated. This RX is compatible with the state-of-the-art reconfigurable Data/Wake-up RX architecture and is ready for SoC integration with digital-intensive back-end processing.