Signal integrity-aware PCB routing for high-speed DRAM module

Abstract

A key for DRAM printed circuit board (PCB) routing is to match length for nets of a bus. The reason is that length mismatch can cause timing propagation delay error of a net, resulting in a bit error. In addition, as data rate of DRAM gets higher, the signal can be affected by various noises during propagation. Signal integrity (SI) should be taken into consideration during length matching. In this paper, we propose a method for DRAM PCB routing considering SI. The routing problem is solved by formulating the routing factors related to SI using a mixed integer quadratically constrained programming (MIQCP) with heuristic algorithms. Due to long time of SI analysis for routing result, SI prediction with a convolutional neural network (CNN) is introduced and a method for rip-up and reroute with CNN information is also proposed. Experimental results show competitive SI results compared to manually routed designs by experienced engineers in much smaller runtime.