Magnetic bloch line racetrack memory bit cell performance analysis with micromagnetics-SPICE hybrid simulations

Abstract

Racetrack memory (RTM) has been a promising candidate for the next-generation non-volatile spintronics memory device. High memory capacity and cost-effectiveness have shown the possibility of replacing hard disk drive and flash memory which are still used as primary memory storage media. However, due to the nature of memory operation through movement between writing and reading processes, there is a characteristic that faultless writing and reading are possible only when highly accurate shift operation is supported. In addition, the non-uniform surface and edge roughness of the nanowire during the process integration make RTM vulnerable to write failure and read failure. These characteristics cause a great deterioration in the reliability of RTM, placing great limitations on their commercialization. This thesis deals with the BL memory, which was proposed to solve the shortcomings of these RTM by structurally improving the degradation due to non-uniform surface conditions. The effect on the entire device area of BL memory was reflected through iterative calculations of SPICE-micromagnetics simulations, and the performance of the bit cell was estimated through Monte Carlo simulations at room temperature.