Machine learning-based error recovery schemes for low latency NAND flash memory system with process variation

Abstract

For high integration and low cost of the NAND flash memory system, advanced multi-leveling and scaling technologies have been introduced. However, as the density of NAND flash memory increases, the cell size becomes smaller, and the interval between threshold voltage distributions decreases, which increases the probability of error occurrence. During the manufacturing process, several memory device parameters vary greatly, which results in significant variations of flash memory reliability. To improve the flash memory reliability, various error recovery schemes have been developed. Typically, the low-density parity-check (LDPC) decoding is a powerful error correction scheme which uses soft-decision information. However, since the optimal LDPC decoding mode is different for each memory chip, an error recovery scheme optimized for each chip is required. In addition, when a model optimized for a specific chip is applied to a chip under different characteristics, performance cannot be guaranteed due to domain shift caused by process variation. For this reason, an approach that ensures high performance in multiple chips by utilizing features which detect process variation is required. In this paper, we propose machine learning-based error recovery schemes which predict the optimal LDPC decoding mode in individual chips and ensure successful error recovery with low latency. Moreover, we show that the prediction performance in multiple chips can be guaranteed by adopting the adversarial discriminative domain adaptation (ADDA), which is a type of transfer learning that generates an encoder adapted to the target domain based on a generative adversarial network (GAN). Simulation results show that the proposed scheme achieves high reliability with low latency by predicting the optimal decoding mode in multiple chips by utilizing the input features which detect process variation.