Ring amplifier-based pipelined ADC with adaptive dead-zone control

Abstract

This thesis presents a ringamp-based, high-speed, high-resolution pipelined ADC without additional off-chip calibration. Typical ringamp-based ADC design requires complex off-chip calibration circuits, which control the dead-zone in the ringamp to optimize ADC performance. Especially, the dead-zone voltage is a critical attribute in the ringamp, which determines both the static and dynamic linearity of the amplifier. The proposed ADC adopts an energy efficient, low complexity dead-zone control scheme, which adaptively modifies dead-zone voltage based on detecting the number of oscillations in ringamp. Since the dead-zone is kept in the optimum range across different PVT conditions, it does not require additional off-chip calibration. This scheme enables a practical ringamp-based ADC design for high-speed, high-resolution applications. The prototype 10-bit 320-MS/s pipelined ADC was implemented in the CMOS-28-nm process and has 0.278-mm2. With Nyquist input, the post-layout simulation signal-to-noise- and-distortion-ratio (SNDR) and spurious-free dynamic range (SFDR) are 53.7-dB and 66.1-dB, respectively consuming 11.62-mW. The ADC achieves 92.3-fJ/conversion step Walden figure-of-merit ($FoM_W$) at 320-MS/s.