FSHMEM

Abstract

Partitioned Global Address Space (PGAS), a parallel programming model that uses a globally shared memory and one-sided communication, has shown promising potential for High-Performance Computing (HPC) applications. At the same time, the HPC community has started to adopt FPGA as an alternative computing framework to the conventional CPU and GPU. However, the exploration of using PGAS along with FPGAs is in a preliminary stage, unlike the message passing model. This work proposes FSHMEM, a software/hardware framework that brings the PGAS programming model to FPGAs. We implement GASNet, a middleware that enables the PGAS programming model, on hardware to provide native PGAS integration on FPGA and the software interface with high compatibility to legacy PGAS programs. Our communication benchmark shows that FSHMEM outperforms prior works by 9.5× by attaining a peak bandwidth of 3813 MB/s, which is 95% of the theoretical maximum. Moreover, the remote write and read operation in FSHMEM has a low latency with an average of 0.35 μs and 0.59 μs, respectively. Lastly, we conducted a case study on two FSHMEM devices implemented on Intel D5005 PACs that contain Intel Deep Learning Accelerator (DLA). This system shows an excellent scalability potential by achieving 1.94× and 1.98× performance gain for parallel matrix-matrix multiplication and convolution, respectively.