DRAM based processing-in-memory architecture for data analytics

Abstract

Data analytics of managing ever-growing datasets in the cloud presents a challenge with the end of Dennard scaling. Moreover, traditional von-Neumann computing architecture exacerbates the “memory wall” problem. To this end, memory-centric architectures, such as near-memory processing (NMP) and processing-in-memory (PIM), are re-emerging as attractive solutions to accelerate data-intensive applications. Especially the memory-centric architecture is a perfect match for data analysis applications because it can significantly improve performance and energy efficiency by reducing data movement. We observe two challenges of prior NMP and PIM architectures when it comes to accelerating data analysis applications. First, NMP architectures limit the performance achievement by leaving the abundant DRAM’s internal bandwidth unutilized. Second, while PIM architectures can exploit DRAM’s internal bandwidth to a greater extent than NMP architectures, integrating computational logic more closely, the abundant internal bandwidth comes at the cost of flexibility in controlling each PIM core. We propose a combined PIM and NMP architecture for accelerating data analytics operations. The architecture is designed considering the properties of data analytics operators and DRAM’s structure. PIM computation cores, buffers, and control circuits are placed across the hierarchical levels of DRAM to exploit the multiple levels of parallelism. The proposed architecture supports multi-threading, where a bank group constitutes a PIM thread, enabling flexible utilization of each thread in parallel. We also propose a new interface for controlling up to 64 PIM threads per rank, enabling programmability of each core with minimized command bottleneck. Compared to baseline CPU architectures, the proposed architecture achieves up to 528x higher throughput and reducing energy consumption by 15.3% than the baseline with only 4.1% additional area overhead.