HBM DRAM architecture based on 8-high full bandwidth stack unit configuration

Abstract

This thesis presents HBM architecture that supports improved memory bandwidth and power efficiency. System-level AI model integration trends that expedite requirements for higher memory bandwidth and HBM architectural factors that limit further memory bandwidth enhancements are introduced. To overcome limitations from standard research methods, 8-High full bandwidth stack unit configuration based on modified 8-High TSV I/O bus and 32-data SerDes schemes that allow 2X channel access utilization and 1X channel data granularity, respectively, is proposed. Evaluation results based on TSV circuitry extraction and power efficiency conversion models confirm 2X bandwidth data mask feasibility and 13.3% power efficiency enhancements compared to previous works.