Analysis of MOSFET degradation with advanced characterization of gate dielectric

Abstract

Since Moore's Law was posited in 1965, the channel length (LG) of field-effect transistors (FETs) has been steadily reduced with the aid of advanced process technology, including lithography technology, and this miniaturization trend still continues. As a result, the chip production cost of logic transistors and memory devices has been reduced, and the operating speed has also continuously increased. However, the reduced LG of the FET increases the horizontal electric field (E-field) across the channel, which transfers high energy to carriers present in the channel during device operation. In addition, as LG decreases, in order to suppress the short-channel effects (SCEs) and minimize leakage current (ILEAK), the physical thickness of the gate dielectric must be reduced, which in turn increases the vertical E-field. Therefore, the horizontal and vertical fields, which have been increased along with miniaturization of the transistor, generate hot-carriers and seriously damage the gate dielectric. Degradation of the gate dielectric includes the generation of interfacial traps occurring at the interface between the dielectric and the substrate, border traps distributed within a certain distance from the interface, and bulk traps that do not react with carriers of the channel but may increase the gate leakage current. The generation of the traps affects the operating current (ION), threshold voltage (VT), and leakage current (ILEAK), which represent the operating characteristics of the device, thereby degrading the device functionality in the circuit operation and increasing variability among devices. Therefore, in order to guarantee stable functionality of a fabricated device and efficiently predict the characteristics, it is necessary to quantitatively analyze trap generation. In this study, the degradation of device characteristics based on off-state stress (OSS) among representative stresses was analyzed with a focus on trap generation. First, vertical profiling was performed along the depth direction of the dielectric of the traps along with a mechanism analysis to determine how OSS degrades devices. In addition, the effect of OSS on the gate-induced drain leakage (GIDL) of the device was analyzed, and horizontal profiling along the channel direction of the generated traps was investigated. On the other hand, synchronized optical charge pumping (SOCP) was devised and applied to a device with a gate-all-around (GAA) structure, to which the traditional charge pumping method cannot be applied, and the density of interfacial traps (Nit) was quantitatively extracted. Furthermore, considering that it is difficult to apply SOCP to the state-of-the-art devices when optical incidence is limited due to gate stacks or metal layering, the GIDL charge pumping method was suggested and the Nit could be extracted. In addition to a technique capable of self-curing the operating characteristics of damaged devices, a method to boost the effect of the self-healing technology by biasing to the gate terminal was studied.