Noise reduction techniques in integrated circuits for communication

Abstract

In this dissertation, noise reduction techniques in integrated circuits for communication is dealt with. In general, it is very important to achieve low noise performance in integrated circuits for communication. On the receiver side, low noise performance is required to achieve low receiver sensitivity. Phase noise (PN) degrades the receiver's signal-to-noise ratio (SNR) through reciprocal mixing with interferers. On the transmitter side, the PN can affect other channels and pollute the EVM in the modulated transmit output, interfering with communication. We propose techniques to achieve low noise performance in terms of receiver and transmitter for smooth communication. On the receiver side, a nested-feedforward noise-canceling (NFF-NC) technique is proposed in a transimpedance amplifier (TIA) for optical communication. The proposed technique minimizes the noise voltages of the second and noise-cancelling (NC) stages of the TIA, significantly improving the noise compared to the conventional NC technique. As a result, the proposed technique shows a noise reduction of 30$\%$ compared to the conventional-NC technique. The proposed NC structure also improves the loop stability by adding LHP zero due to the feedforward (FF) stage. The proposed NFF-NC TIA was fabricated in a 65 nm CMOS process and consumes 10.1 mW of power from 1.3 V supply. The proposed TIA achieves a dc transimpedance gain of 56.3 dB and a 3 dB bandwidth (BW) of 6.5 GHz. The average input noise current density ($\overline{i_{n,in,avg}}$) is 15.1 $pA/\sqrt{Hz}$. Eye diagrams were also measured for a pseudo-random binary sequence of $2^7-1$ with a data rate of 8.5 Gb/s. Compared to previous TIAs with similar data rates, the highest levels of noise and FoM are achieved. From the transmitter point of view, a FS for UHF RFID reader SoC is introduced. Transmitter noise performance is very important to meet the stringent spectrum mask and spurious emission requirements of UHF RFID reader SoCs. PN of the FS is the most dominant performance in transmitter noise. The FS is proposed to satisfy the target specifications for the UHF RFID reader application which is designed with a narrow loop BW and a $2^{nd}$-order loop filter with a new low-noise VCO topology. The proposed VCO simultaneously exhibits the noise circulation and gate-to-drain skew manipulation mechanism, and thus achieves low thermal and flicker PN. The FS was integrated in 55nm CMOS process along with the UHF RFID reader transmitter and consumes 10.16 mW of power. The proposed VCO achieves the highest level of FoM at 10 kHz offset frequency compared to previous VCOs operating at similar frequencies. The proposed CPPLL achieves the lowest PN and low power among FS targeting UHF RFID reader SoC, and also achieves the lowest PN and FoM at 1.8 MHz offset frequency compared to recently published state-of-the-art FS.