Study on power converter with noise reduction and reduced voltage stress

Abstract

In this dissertation, a novel power converter circuit with noise reduction and reduced voltage stress is proposed. By minimizing the current ripple at the input and output terminals of the converter, the size of the filter can be reduced along with noise reduction, and by reducing the voltage stress of the semiconductor switching device, the performance and efficiency of the converter can be improved. The first proposed circuit is a resonant DC-DC converter circuit with a small input current ripple, which can improve the input noise of the conventional converter by reducing the input current ripple, as well as reduce the conduction loss by reducing the voltage stress of the diode. Moreover, it has the advantage of reducing the switching loss of switches and diodes through the soft switching operation. The second one is a new 13-level switched capacitor inverter circuit with reduced voltage stress. It can reduce the output harmonic by outputting a 13-level waveform. In addition, the voltage stress of all switches is kept less than half of the output maximum voltage, reducing power loss. Moreover, due to having a high voltage boost ability, it can be a single-stage structure by removing the DC-DC boost converter of the conventional two-stage inverter and has also the advantage of reducing the cost and the number of switches.