Analysis and Design of Power-Efficient H-Band CMOS Frequency Doubler Employing Gain Boosting and Harmonic Enhancing Techniques

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This article presents a power-efficient frequency doubler employing gain boosting and harmonic-enhancing techniques. With a single transistor only, the gain boosting technique can reach the maximum achievable gain (G(max)) by adding embedded passive components, thereby obtaining high voltage swings. Then, the transistor's nonlinearity is essential, which is maximized by the harmonic transition scheme of the transistor operation along with high voltage swings. In addition, a harmonic reflector and a harmonic leakage canceller are employed for the second harmonic enhancement. The harmonic reflector prevents unwanted harmonic mixing by minimizing the incoming second harmonic current fed back to the input. The harmonic leakage canceller suppresses the leakage loss of the second harmonic current present at the output. Furthermore, thanks to a proposed dual-band output matching network, the output impedance is conjugately matched to achieve the G(max) at the fundamental frequency while it is matched to extract the second harmonic output power simultaneously. To verify the proposed techniques, the prototype was designed as a single-stage circuit that does not require additional amplifying stages, which led to higher power efficiency and lower chip area. Implemented in a 65-nm CMOS process, the measurement results show a saturated output power of 0.9 dBm and 3-dB bandwidth of 26 GHz (237-263 GHz), respectively, while requiring a chip area of 0.071 mm(2). Total power efficiency, including the effect of injected signal power, is 2.87 % while consuming only 37 mW dc power.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2023
Language
English
Article Type
Article
Citation

IEEE ACCESS, v.11, pp.34942 - 34951

ISSN
2169-3536
DOI
10.1109/ACCESS.2023.3264531
URI
http://hdl.handle.net/10203/306798
Appears in Collection
EE-Journal Papers(저널논문)
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