A 60-GHz Variable-Gain Phase Shifter With an Active RL Poly-Phase Filter

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dc.contributor.authorSo, Cheolko
dc.contributor.authorSung, Euntaekko
dc.contributor.authorHong, Songcheolko
dc.date.accessioned2023-03-03T09:16:29Z-
dc.date.available2023-03-03T09:16:29Z-
dc.date.created2022-11-23-
dc.date.created2022-11-23-
dc.date.issued2023-02-
dc.identifier.citationIEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, v.71, no.2, pp.593 - 601-
dc.identifier.issn0018-9480-
dc.identifier.urihttp://hdl.handle.net/10203/305451-
dc.description.abstractA 60-GHz variable-gain phase shifter consisting of an active I/Q generator and Gilbert-cell-based summing amplifier fabricated in a 65-nm bulk CMOS process is presented here. The proposed I/Q signal generator is implemented by inserting an RL poly-phase filter into the interstage node of a cascode amplifier, which provides good interstage matching and results in a finite gain in the I/Q generator. It also provides good isolation characteristics between the I/Q generator and the subsequent vector-summing amplifier due to the common gate buffer stages. Therefore, it minimizes the rms gain and phase errors of the phase shifter by maintaining accurate I/Q signals regardless of the input impedance of the vector-summing amplifier, which varies with the gain and phase states. The vector-summing amplifier is operated by a current-steering digital to analog converter (DAC) to keep the total dc current constant regardless of the gain and phase states, which makes the output return loss constant. The DAC makes the vector-summing amplifier generate an arbitrary vector by determining the sizes of the I and Q vectors, and the double pole, double throw (DPDT) switch determines the quadrants. The rms gain and phase errors of the proposed variable-gain phase shifter show the values of 0.13 dB and 0.36<inline-formula> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula>, respectively, at 60 GHz with 4-bit gain control in a 20-dB dynamic range and 5-bit phase control at 360<inline-formula> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula>. In the 3-dB frequency range of 56.8–64.1 GHz, the rms gain and phase error outcomes are 0.26 dB and 1.44<inline-formula> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula>, respectively. The chip area and overall power consumption are measured and found to be 0.55 mm<inline-formula> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> and 14.52 mW, respectively.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleA 60-GHz Variable-Gain Phase Shifter With an Active RL Poly-Phase Filter-
dc.typeArticle-
dc.identifier.wosid000934999700012-
dc.identifier.scopusid2-s2.0-85141444271-
dc.type.rimsART-
dc.citation.volume71-
dc.citation.issue2-
dc.citation.beginningpage593-
dc.citation.endingpage601-
dc.citation.publicationnameIEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES-
dc.identifier.doi10.1109/TMTT.2022.3214814-
dc.contributor.localauthorHong, Songcheol-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorGenerators-
dc.subject.keywordAuthorGain-
dc.subject.keywordAuthorPhase shifters-
dc.subject.keywordAuthorLogic gates-
dc.subject.keywordAuthorImpedance-
dc.subject.keywordAuthorPhased arrays-
dc.subject.keywordAuthorBaluns-
dc.subject.keywordAuthorActive RL poly-phase filter-
dc.subject.keywordAuthorCMOS-
dc.subject.keywordAuthordigital to analog converter (DAC)-
dc.subject.keywordAuthormillimeter-wave (mm-wave)-
dc.subject.keywordAuthorphase shifter-
dc.subject.keywordAuthorV-band-
dc.subject.keywordAuthorvariable-gain-
dc.subject.keywordPlusSIGE BICMOS-
dc.subject.keywordPlusARRAY TRANSMITTER-
dc.subject.keywordPlusFMCW RADAR-
dc.subject.keywordPlusBAND-
dc.subject.keywordPlusCMOS-
dc.subject.keywordPlusTRANSCEIVER-
dc.subject.keywordPlusAMPLIFIER-
dc.subject.keywordPlusDESIGN-
dc.subject.keywordPlusRANGE-
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