An Output-Capacitorless Analog LDO Featuring Frequency Compensation of Four-Stage Amplifier

Abstract

In this paper, we propose an output-capacitorless analog low-dropout voltage regulator (ALDO) featuring frequency compensation of a four-stage amplifier consisting of a three-stage error amplifier (EA) without cascoding plus a last stage formed by a pass transistor (M-p). It achieves good output voltage regulation under low supply-voltage (V-dd) with an unsaturated M-p (e.g., dropout voltage of 30 mV under 0.5 V supply) because of the three gain stages in the EA. Frequency compensation is achieved by performing a two-port feedback analysis with the root-locus diagram (TFR) method that provides an intuitive understanding of pole/zero dynamics in the s-plane. Fabricated in 0.18 gm CMOS, the proposed ALDO achieves asymptotic stability over a wide range of operating conditions: V-dd of 0.5 similar to 1.8 V, load capacitance of 0 similar to 50 pF, load current (I-L) of 0 similar to 2 mA (0 similar to 200 mA) under V-dd of 0.5 V (1.8 V), and temperature of -20 similar to 125 degrees C. Also, it does not require minimum on-chip output capacitance, thus achieving a small area of 0.0035 mm(2). As a result, a good low-frequency PSR of -62 dB with a dropout voltage of 30 mV and a state-of-the-art current density of 11.4 A/mm(2) are achieved.