Decoupling Capacitor Insertion Minimizing IR-Drop Violations and Routing DRVs

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dc.contributor.authorHyun, Daijoonko
dc.contributor.authorJung, Younggwangko
dc.contributor.authorCho, Insuko
dc.contributor.authorShin, Youngsooko
dc.date.accessioned2023-02-08T03:00:30Z-
dc.date.available2023-02-08T03:00:30Z-
dc.date.created2022-11-22-
dc.date.created2022-11-22-
dc.date.issued2023-01-17-
dc.identifier.citation28th Asia and South Pacific Design Automation Conference (ASP-DAC 2023), pp.271 - 276-
dc.identifier.urihttp://hdl.handle.net/10203/305097-
dc.description.abstractDecoupling capacitor (decap) cells are inserted near function cells of high switching activities so that their IR-drop can be suppressed. Their design becomes more complex and uses higher metal layers, thereby starting to manifest themselves as routing blockage. Postplacement decap insertion, with a goal of minimizing both IR-drop violations and routing design rule violations (DRVs), is addressed for the first time. U-Net with graph convolutional network is introduced to predict routing DRV penalty. The decap insertion problem is formulated and a heuristic algorithm is presented. Experiments with a few test circuits demonstrate that DRVs are reduced by 16% on average with no IR-drop violations, compared to a conventional method which does not explicitly consider DRVs. This results in 48% reduction in routing runtime and 23% improvement in total negative slack.-
dc.languageEnglish-
dc.publisherAssociation for Computing Machinary, Inc.-
dc.titleDecoupling Capacitor Insertion Minimizing IR-Drop Violations and Routing DRVs-
dc.typeConference-
dc.identifier.scopusid2-s2.0-85148488088-
dc.type.rimsCONF-
dc.citation.beginningpage271-
dc.citation.endingpage276-
dc.citation.publicationname28th Asia and South Pacific Design Automation Conference (ASP-DAC 2023)-
dc.identifier.conferencecountryJA-
dc.identifier.conferencelocationTokyo Odaiba Miraikan-
dc.identifier.doi10.1145/3566097.3567905-
dc.contributor.localauthorShin, Youngsoo-
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EE-Conference Papers(학술회의논문)
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