DC Field | Value | Language |
---|---|---|
dc.contributor.author | Park, Suneui | ko |
dc.contributor.author | Yoo, Seyeon | ko |
dc.contributor.author | Shin, Yuhwan | ko |
dc.contributor.author | Lee, Jeonghyun | ko |
dc.contributor.author | Choi, Jaehyouk | ko |
dc.date.accessioned | 2023-02-03T01:01:50Z | - |
dc.date.available | 2023-02-03T01:01:50Z | - |
dc.date.created | 2022-11-01 | - |
dc.date.issued | 2023-01 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.58, no.1, pp.78 - 89 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/304995 | - |
dc.description.abstract | This work presents an ultralow-jitter ring-oscillator (RO)-based injection-locked clock multiplier (ILCM). Using the power-gating (PG) injection method that can completely remove the accumulated phase error of the RO, the proposed ILCM can achieve a very wide injection bandwidth, and, thus, an ultralow-jitter, even when the multiplication factor, N, is increased above 60. To overcome the natural limitation of the PG injection, two digitally controlled oscillators (DCOs) were used to operate in a complementary manner. Since the background multi-functional calibrator (MFC) continuously synchronizes the outputs of the two DCOs, the PG-ILCM can generate a seamless output signal by combining these two signals. The proposed injection pulsewidth controller (IPWC) decreased the required delay of the digital-to-time converter (DTC), further reducing the jitter of the output signal. A phase-rotational divide-by-4 divider (PR-DIV4) also was proposed to reduce the operating frequency and the power consumption of the MFC while maintaining the fine resolution of the output frequency. The PG-ILCM, fabricated in a 65-om CMOS process, used the power of 143 mW and an area of 0.102 mm(2). The rms jitter measured at 8.16 GHz (N = 68) was 97 fs. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68 | - |
dc.type | Article | - |
dc.identifier.wosid | 000869040000001 | - |
dc.identifier.scopusid | 2-s2.0-85139879101 | - |
dc.type.rims | ART | - |
dc.citation.volume | 58 | - |
dc.citation.issue | 1 | - |
dc.citation.beginningpage | 78 | - |
dc.citation.endingpage | 89 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/JSSC.2022.3210212 | - |
dc.contributor.localauthor | Choi, Jaehyouk | - |
dc.contributor.nonIdAuthor | Yoo, Seyeon | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Calibrator | - |
dc.subject.keywordAuthor | injection-locked clock multiplier (ILCM) | - |
dc.subject.keywordAuthor | phase noise | - |
dc.subject.keywordAuthor | power-gating (PG) | - |
dc.subject.keywordAuthor | ring oscillator (RO) | - |
dc.subject.keywordAuthor | rms jitter | - |
dc.subject.keywordPlus | LOOP | - |
dc.subject.keywordPlus | DESIGN | - |
dc.subject.keywordPlus | PLL | - |
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