Modeling and Signal Integrity Analysis of Mounting Pad with Layer-cutting to reduce Impedance Mismatch for Dual-In-Line Memory Module (DIMM)

Abstract

In this paper, we modeled and analyzed the layer-cutting structure for the mounting pad. We conduct electrical modeling of the layer-cutting structure for the impedance matching. Through the proposed modeling, an accurate impedance can be calculated considering the fringing capacitance. The proposed modeling is verified by comparison with the electromagnetic (EM) simulation. Based on the proposed modeling, it is possible to achieve impedance matching to improve signal integrity. In addition, signal integrity analysis is performed on the mounting pad in the dual-in-line-memory module (DIMM) board with the layer cutting technique based on the insertion loss and impedance.