Method of reducing device parasitic capacitance using underneath crystallographically selective wet etching

Abstract

When InP DHBTs are located in parallel to a crystallographical direction of 003c#011003e#, there are several advantages in the aspect of device property such as reliability. But, in case of a direction parallel to a general 003c#011003e#, there exists the limitation in reducing base-collector parasitic capacitance only by collector over-etching technique due to poor lateral-etching characteristic of the InP collector. To overcome such a problem mentioned above and improve device performance, the present invention provides a method of reducing parasitic capacitance using underneath crystallographically selective wet etching, thereby providing a self-alignable, structurally stable device.