Prediction of highly imbalanced semiconductor chip-level defects using uncertainty-based adaptive margin learning

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In semiconductor manufacturing, the package test is a process that verifies whether the product specifications are satisfied before the semiconductor products are finally shipped to customers. The packaged chips are classified as good or defective according to the verification results. To ensure high-quality products and customer satisfaction, it is important to detect defective chips during the package test. In this article, we consider the problem of predicting potential defects in advance using the wafer-test results data obtained from an earlier stage of the wafer test. There are several challenges in this problem. First, package-test data are highly class-imbalanced with a very low defect rate, and the imbalance level may vary due to the variability in manufacturing processes. Second, there is a complex relationship between package- and wafer-test results. Third, it is more important to increase the detection accuracy of defects than the overall classification accuracy. To address these challenges, we propose a Bayesian-neural-network-based prediction model. The proposed model adaptively considers unknown imbalance levels through the flexible adjustment of the decision boundary by using class- and sample-level prediction uncertainties and the relative frequency of each class. Using a real semiconductor manufacturing dataset from a global semiconductor company, we demonstrate that the proposed model can effectively predict defects even when the imbalance level of the test dataset differs from that of the training dataset.
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IISE TRANSACTIONS, v.55, no.2, pp.147 - 155

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IE-Journal Papers(저널논문)
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