A Single-Supply Single-Core Inverse Class-D Digital Power Amplifier with Enhanced Power Back-Off Efficiency Adopting Output Power Scaling Technique
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Choi, Kyungsik | ko |
| dc.contributor.author | Ko, Jinho | ko |
| dc.contributor.author | Lee, Sang-Gug | ko |
| dc.date.accessioned | 2022-11-29T06:01:46Z | - |
| dc.date.available | 2022-11-29T06:01:46Z | - |
| dc.date.created | 2022-11-28 | - |
| dc.date.issued | 2021-06 | - |
| dc.identifier.citation | 35th Symposium on VLSI Circuits, VLSI Circuits 2021 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/301236 | - |
| dc.description.abstract | This work presents a current-mode inverse Class-D digital PA (DPA) with enhanced power back-off (PBO) efficiency. The PA adopts extra switches, which allows the scaling in the output voltage swing by half, leading to (theoretically) 6 dB enhancement in PBO efficiency while maintaining (ideally) 100% drain efficiency (DE). Implemented in a 65 nm CMOS, the proposed DPA shows the improvement in DE by ×1.5 at 4.2 dB PBO in comparison with normalized Class-B PA while requiring only one transformer and single-supply voltage. | - |
| dc.language | English | - |
| dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
| dc.title | A Single-Supply Single-Core Inverse Class-D Digital Power Amplifier with Enhanced Power Back-Off Efficiency Adopting Output Power Scaling Technique | - |
| dc.type | Conference | - |
| dc.identifier.scopusid | 2-s2.0-85111814108 | - |
| dc.type.rims | CONF | - |
| dc.citation.publicationname | 35th Symposium on VLSI Circuits, VLSI Circuits 2021 | - |
| dc.identifier.conferencecountry | JA | - |
| dc.identifier.conferencelocation | Virtual | - |
| dc.identifier.doi | 10.23919/VLSICircuits52068.2021.9492341 | - |
| dc.contributor.localauthor | Lee, Sang-Gug | - |
| dc.contributor.nonIdAuthor | Ko, Jinho | - |
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