A 237-263 GHz CMOS Frequency Doubler with 0.9 dBm Output Power and 2.87 % Power Efficiency Based on Harmonic Matched Gmax-Core

Abstract

This work presents a power-efficient frequency doubler based on a harmonic matched maximum achievable gain ($G_{\max}$) core. The harmonic matched $G_{\max}$-core satisfies the $G_{\max}$ condition for the maximum fundamental signal, which increases the harmonic signal due to a nonlinear function of a transistor. In addition, to enhance the harmonic signal level, the undesired harmonic feedback signal and harmonic leakage are suppressed at the input and output of the $G_{\max}$-core by adopting a harmonic reflector and a harmonic leakage canceller, respectively. This enhanced harmonic signal from the harmonic matched $G_{\max}$-core is extracted by adopting the dual-band (fundamental and harmonic) output matching network and therefore maintaining the $G_{\max}$ condition at the fundamental frequency. The proposed frequency doubler is implemented in a single stage without requiring amplifying stages. Implemented in a 65-nm CMOS, measurement results show the maximum saturated output power of 0.9 dBm and 3-dB bandwidth of 26 GHz (237-263 GHz) while requiring the chip area of 0.071 mm2. The total power efficiency that includes the input signal power is 2.87 % while consuming only 37 mW dc power.