FACTGen: Framework for Automated Circuit Topology Generator
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Suh, Jangwon | ko |
| dc.contributor.author | Jung, Wanyeong | ko |
| dc.date.accessioned | 2022-11-28T08:02:46Z | - |
| dc.date.available | 2022-11-28T08:02:46Z | - |
| dc.date.created | 2022-11-27 | - |
| dc.date.created | 2022-11-27 | - |
| dc.date.created | 2022-11-27 | - |
| dc.date.issued | 2022-10-20 | - |
| dc.identifier.citation | 19th International SoC Conference, ISOCC 2022 | - |
| dc.identifier.issn | 2163-9612 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/301167 | - |
| dc.description.abstract | Besides the popularity of computer-aided design methods, the circuit topology design itself still relies on human insights. We propose a framework for automated circuit topology generator (FACTGen). Our framework transforms the circuit topology generation problem into a continuous black-box optimization problem. FACTGen has succeeded to generate several 2T and 4T CMOS digital gate topologies. | - |
| dc.language | English | - |
| dc.publisher | The Institute of Semiconductor Engineers | - |
| dc.title | FACTGen: Framework for Automated Circuit Topology Generator | - |
| dc.type | Conference | - |
| dc.identifier.wosid | 000971297000014 | - |
| dc.identifier.scopusid | 2-s2.0-85148454612 | - |
| dc.type.rims | CONF | - |
| dc.citation.publicationname | 19th International SoC Conference, ISOCC 2022 | - |
| dc.identifier.conferencecountry | KO | - |
| dc.identifier.conferencelocation | Virtual | - |
| dc.contributor.localauthor | Jung, Wanyeong | - |
- Appears in Collection
- EE-Conference Papers(학술회의논문)
- Files in This Item
- There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.