An Adaptive Clocking System using Supply Tracking Clock Modulator with Background Calibrated Supply-Sensitivity in 28nm CMOS

Abstract

Clock frequency of microprocessors must be low enough to ensure error-free operation under supply fluctuation. As having a fixed, low-frequency clock results in sub-par performance, previous works have proposed adaptive clocking (AC) where logic blocks receive reduced clock frequency from the PLL when there is supply droop [1–5]. Unfortunately, there is a couple of issues that limit the performance of the AC. First, previous works employ ACs before the clock buffer and thus do not consider the delay of the clock buffer from the PLL output to the logic blocks that could be up to ten clock cycles at GHz clock frequencies [1]. Due to this delay, the logic block may not receive the correctly adjusted clock when there is supply droop as shown in Fig. 1(a). Second, previous ACs achieve limited performance as the reduced clock frequency is either a fixed or coarsely quantized value [1–4], and does not adapt optimally to the supply [5]. To address these issues, we present a background calibrated supply tracking clock modulator (STCM) that optimally adjusts the clock frequency to the supply by placing it at the end of the clock buffer, instead of before.