DC Field | Value | Language |
---|---|---|
dc.contributor.author | Cho, Jeong-Hyun | ko |
dc.contributor.author | Kim, Dong-Kyu | ko |
dc.contributor.author | Bae, Hong-Hyun | ko |
dc.contributor.author | Lee, Yong-Jin | ko |
dc.contributor.author | Koh, Seok-Tae | ko |
dc.contributor.author | Choo, Younghwan | ko |
dc.contributor.author | Paek, Ji-Seon | ko |
dc.contributor.author | Kim, Hyun-Sik | ko |
dc.date.accessioned | 2022-11-17T06:02:11Z | - |
dc.date.available | 2022-11-17T06:02:11Z | - |
dc.date.created | 2022-09-27 | - |
dc.date.created | 2022-09-27 | - |
dc.date.issued | 2022-02 | - |
dc.identifier.citation | 2022 IEEE International Solid-State Circuits Conference, ISSCC 2022, pp.298 - 300 | - |
dc.identifier.issn | 0193-6530 | - |
dc.identifier.uri | http://hdl.handle.net/10203/299799 | - |
dc.description.abstract | For more efficient power management in processors, a high-frequency and multi-phase (MP) integrated voltage regulator (IVR) using multiple inductors would be an ideal solution to deliver optimized power with rapid dynamic voltage scaling (DVS) [1]-[5]. Nevertheless, in practical use, MP-IVRs suffer from an inter-inductor current imbalance because of mismatches in integrated inductances, different parasitic resistances, and duty-control skews among all phases (top of Fig. 18.1.1). Such a current mismatch may cause larger output ripple and efficiency degradation, losing the benefits of multi-phase operation. Also, thermal hotspots can occur due to excessive current density and deteriorate reliability. Previous approaches [2], [4] use current sensors to calibrate the duty cycle of each phase, but the design complexity and power overhead tend to be greatly increased in the high-speed sensing circuitry for fast-switching converters. An additional consideration in MP-IVRs is the phase-shedding technique, which can improve the light-load efficiency by reducing the number of phases. In many prior works [1], [2], the number of phases was adjusted by 2N (e.g., 1-2-4) for simplicity of phase division. If the phase-shedding is more fine-grained, the overall efficiency can be more flattened over a wide range of loads. Moreover, because the frequency response and output ripple vary according to the number of phases, the MP-IVR should be adaptively optimized further for them. This paper presents a 400MHz 6-phase fully integrated buck converter (bottom of Fig. 18.1.1). Key contributions of this work include 1) inter-inductor true-average-current matching by the flying-capacitor-based peak-and-valley differential sensing (PVDS) technique with near-zero power overhead, 2) area-efficient dynamic re-allocation of on-chip capacitors used either in the PVDS or at the output for optimizing responsiveness and voltage ripple adaptively to the number of phases, and 3) DLL -based multi-phase clock generation (MPCG) for fine-grained phase-shedding functionality, improving efficiency over a wide load range. | - |
dc.language | English | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | A 1.23W/mm283.7%-Efficiency 400MHz 6-Phase Fully Integrated Buck Converter in 28nm CMOS with On-Chip Capacitor Dynamic Re-Allocation for Inter-Inductor Current Balancing and Fast DVS of 75mV/ns | - |
dc.type | Conference | - |
dc.identifier.scopusid | 2-s2.0-85128253052 | - |
dc.type.rims | CONF | - |
dc.citation.beginningpage | 298 | - |
dc.citation.endingpage | 300 | - |
dc.citation.publicationname | 2022 IEEE International Solid-State Circuits Conference, ISSCC 2022 | - |
dc.identifier.conferencecountry | US | - |
dc.identifier.conferencelocation | San Francisco | - |
dc.identifier.doi | 10.1109/ISSCC42614.2022.9731726 | - |
dc.contributor.localauthor | Kim, Hyun-Sik | - |
dc.contributor.nonIdAuthor | Kim, Dong-Kyu | - |
dc.contributor.nonIdAuthor | Choo, Younghwan | - |
dc.contributor.nonIdAuthor | Paek, Ji-Seon | - |
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